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Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Integrated Interface Block for PCI Express Designs Switching Characteristics
More information and documentation on solutions for PCI Express designs can be found at:
http://www.xilinx.com/technology/protocols/pciexpress.htm
Table 39: Maximum Performance for PCI Express Designs
Symbol
Description
-3
Speed Grade
-2 -1
-1L
Units
F PIPECLK
F USERCLK
F DRPCLK
Pipe clock maximum frequency
User clock maximum frequency
DRP clock maximum frequency
250
500
250
250
500
250
250
250
250
250
250
250
MHz
MHz
MHz
System Monitor Analog-to-Digital Converter Specification
Table 40: Analog-to-Digital Specifications
Parameter
Symbol
Comments/Conditions
Min
Typ
Max
Units
AV DD = 2.5V ± 5%, V REFP = 1.25V, V REFN = 0V, ADCCLK = 5.2 MHz, T j = –55°C to 125°C M-Grade, Typical values at T j =+35°C
DC Accuracy: All external input channels. Both unipolar and bipolar modes.
Resolution
10
–
–
Bits
Integral Nonlinearity
INL
–
–
±1
LSBs
Differential Nonlinearity
DNL
No missing codes (T MIN to T MAX )
–
–
±0.9
LSBs
Guaranteed Monotonic
Unipolar Offset Error (1)
Uncalibrated
–
±2
±30
LSBs
Bipolar Offset Error
Gain Error
(1)
Uncalibrated measured in bipolar mode
Uncalibrated - External Reference
Uncalibrated - Internal Reference
–
–
–
±2
±0.2
±2
±30
±2
–
LSBs
%
%
Bipolar Gain Error
(1)
Uncalibrated - External Reference
Uncalibrated - Internal Reference
–
–
±0.2
±2
±2
–
%
%
Total Unadjusted Error
TUE
Deviation from ideal transfer function.
–
±10
–
LSBs
(Uncalibrated)
External 1.25V reference
Deviation from ideal transfer function.
–
±20
–
LSBs
Internal reference
Total Unadjusted Error
TUE
Deviation from ideal transfer function.
–
±1
±2
LSBs
(Calibrated)
External 1.25V reference
Calibrated Gain Temperature
Variation of FS code with temperature
–
±0.01
–
LSB/°C
Coefficient
DC Common-Mode Reject
CMRR DC
V N = V CM = 0.5V ± 0.5V,
V P – V N = 100mV
–
70
–
dB
Conversion Rate (2)
Conversion Time - Continuous
Conversion Time - Event
T/H Acquisition Time
t CONV
t CONV
t ACQ
Number of CLK cycles
Number of CLK cycles
Number of CLK cycles
26
–
4
–
–
–
32
21
–
DRP Clock Frequency
ADC Clock Frequency
CLK Duty cycle
DCLK
ADCCLK
DRP clock frequency
Derived from DCLK
8
1
40
–
–
–
80
5.2
60
MHz
MHz
%
DS152 (v3.6) March 18, 2014
Product Specification
www.xilinx.com
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